Dynamic random access memory (DRAM) is a widely utilized type of high density volatile memory. In the ongoing effort to achieve ever higher memory densities, a one transistor DRAM cell has been developed. In one approach, an individual memory cell is provided on a silicon on insulator (SOI) substrate that includes only a single transistor, and does not include a capacitor. This type of DRAM cell, also known as a capacitorless DRAM cell because it does not require a capacitor, and is commonly implemented as an n-channel silicon on insulator device.
The n-channel silicon on insulator one transistor DRAM cells in general use typically include a gate situated over the channel region of the transistor in which minority charge carriers (holes in the case of an n-channel device) are sequestered in the channel during programming. The one transistor DRAM cell can be programmed to a logic “1” or a logic “0” by appropriately biasing the gate, the semiconductor substrate underlying the buried oxide (BOX) layer contributing to electrical isolation of the channel, and the doped silicon source and drain regions of the DRAM cell. As a result of the programming operation, the accumulated holes in the channel float and remain in the channel since the underlying layer is an insulator. The effect of the accumulated and floating holes in the channel is to change the threshold voltage of the transistor, thus indicating that the transistor has been programmed. A read operation may be performed by sensing the gate voltage or the drain current to determine if the one transistor DRAM cell is programmed as a logic “1” or a logic “0.”
The difference in gate voltage or drain current between a logic “1” and a logic “0” may be referred to as the sensing margin of the one transistor DRAM cell. In the silicon on insulator one transistor DRAM cells commonly in use today, the sensing margin is generally considered to be too low. One conventional approach to compensate for the low sensing margins seen in present silicon on insulator one transistor DRAM cells requires complicated sensing circuitry to distinguish a logic “1” from a logic “0” A significant drawback of this approach, however, is that providing the sensing circuitry can undesirably increase manufacturing cost.
Another conventional approach to the problem of low sensing margins in silicon on insulator one transistor DRAM cells, requires application of high biasing voltages, when compared to operational voltages applied to logic devices that may be co-located on a semiconductor die. Those logic devices may have operating voltages of approximately 1.0 V, while as much as approximately 2.4V may be required to produce adequate sensing margins in the silicon on insulator one transistor memory cells. Consequently this second approach imposes several significant disadvantages as well. First, the one transistor memory cells operating under these elevated biasing conditions are working at or near their voltage limits, making device reliability an issue. Secondly, the elevated voltages required to program the memory cells are potentially damaging to logic devices sharing the semiconductor die, requiring separate voltage sources and separate metal lines for application of the higher voltages to the memory cells. In addition, the elevated voltages required by conventional silicon on insulator one transistor memory cells may require the use of charge pumps to sustain the high biasing voltages, adding further to the complexity and the cost of this conventional solution.
Thus, there is a need in the art to overcome the drawbacks and deficiencies of the conventional one transistor memory cell.